1. Field of the Invention
The present invention relates to a member for a semiconductor package and a semiconductor package using the same, and more particularly to a member for a semiconductor package capable of connecting chip pads provided in the semiconductor chip to external terminals, and a semiconductor package using the above member which approximates the size of the semiconductor chip.
2. Description of the Conventional Art
One of the most general types among various kinds of semiconductor packages is formed such that a semiconductor chip is fixedly attached to paddles of a lead frame, pads of the chip are electrically connected with internal leads of the lead frame and the resultant structure is sealed by a molding resin.
FIG. 1 is a cross-sectional diagram illustrating a small outline J-lead (SOJ) semiconductor package, among conventional semiconductor packages, in which each outer leads has a xe2x80x9cJxe2x80x9d shape.
As shown therein, internal leads 3 of a lead frame are adherent to both sides of an upper surface of a semiconductor chip 1 by an adhesive 2, and chip pads 6 formed on a center portions of the upper surface of the chip 1 are connected with the internal leads 3 by virtue of wires 4 in an ultra-sound heat compression mode. The semiconductor chip 1 and the internal leads 3 are sealed by a molding resin 5, excluding outer leads 7. Then, the outer leads 7 are formed according to the purpose of a user. In the diagram, the external leads 7 are formed in the xe2x80x9cJxe2x80x9d shape.
However, the above conventional semiconductor package, in which electric signals from the chip pads 6 of the semiconductor chip 1 are supplied to external terminals of the package by using the internal and external leads 3, 7 of the lead frame, has a package size which is considerably larger than the semiconductor chip size and has relatively long electric paths between the chip pads 6 and the corresponding external leads 7, which results in deterioration of electric properties and difficult fabrication of a high-pin semiconductor package.
Accordingly, to make up for disadvantages of the conventional semiconductor package provided with the above-mentioned lead frame, various kinds of semiconductor packages have been developed and a chip size semiconductor package is one of the most improved semiconductor packages.
FIG. 2 is a perspective view of a ball grid array (BGA) semiconductor package of the chip size semiconductor packages. With reference to FIG. 2, the conventional BGA semiconductor package is fabricated by, via a pre-assembly process, providing metal wires 13 for electrically connecting a plurality of chip pads 12 with corresponding internal-bump pads 17 which are provided on a semiconductor chip 11, attaching conductive internal bumps 16 on the corresponding internal-bump pads 17 which respectively have a tape (not shown) thereon, sealing the resultant semiconductor chip with a molding resin 14, exposing an upper surface of each internal bump 16 by removing the tape, applying solder paste and conductive external bumps 15 onto the internal bumps 16, and attaching the external bumps 15 to the corresponding internal bumps 16 through an infrared reflow process.
Further, FIG. 3 is a cross-sectional view of the conventional BGA semiconductor package shown in FIG. 2, wherein the chip pad 12 is arranged on the upper surface of the semiconductor chip 11, a protection film 18 for protecting the chip 12 is provided on the semiconductor chip 11 excluding an upper surface of the chip pad 12, the metal wire pattern 13 is provided on the protection film 18 including the chip pad 12 portion which is exposed, and one end of the metal wire 13 is connected with the chip pad 12 while the other end thereof to the internal-bump pad 17.
In addition to the above structure, on the above structure excluding the portion of the internal-bump pad 17 a polyimide film 19 is provided, the internal bump 16 is attached on the exposed pad 17 by a solder adhesive 20 such as Pb or Sn, the entire surface excluding the upper surface of the internal bump 16 is sealed by a molding resin 14 to cover the semiconductor chip 11, and the ball-type external bump 15 is attached onto the internal bump 16.
In the above BGA chip size semiconductor package, a bump pattern is provided on the semiconductor chip 11 to transfer an electric signal from the chip pad 12 to the external bump 15 by performing a separate pre-assembly process.
In other words, from the chip pad 12 to the internal-bump pad 17 of the semiconductor chip 11 the metal pattern 13 is formed for the electric connection therebetween, the conductive internal bump 16 is attached onto the internal-bump pad 17, then the resultant semiconductor chip 11 is sealed by the molding resin 14 and the external bump 15, serving as the external lead, is attached on the internal bump 16.
However, although the thusly provided BGA semiconductor package has a smaller package size to the chip size than the conventional semiconductor package shown in FIG. 1, it is required to have the internal and external bump attaching processes and the pre-assembly process which results in high-cost of the fabrication thereof.
Accordingly, the present invention is directed to a member for a semiconductor package which obviates the problems and disadvantages the conventional art.
An object of the present invention is to provide a member for a semiconductor package which facilitates the structure of a high-pin semiconductor package and simplifies the fabrication process by excluding an internal bump attaching process.
Another object of the present invention is to provide a chip size semiconductor package which is an ultra-thin size and a fabrication method thereof by applying the member for the semiconductor package.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the member for the semiconductor package is provided with an insulation film; predetermined conductive wire patterns formed to a lower surface of said insulation film; and first and second openings formed in the insulation film to at least partially expose the conductive patterns.
Further, a semiconductor package according to the present invention includes an insulation film; predetermined conductive wire patterns formed to a lower surface of said insulation film; first and second openings formed in the insulation film to at least partially expose the conductive patterns; a semiconductor chip wherein end portions of conductive wire patterns under the first openings are attached to corresponding chip pads provided on the chip; a filling material for sealing the first openings; and external terminals attached onto the corresponding conductive wire patterns which are exposed to the second openings.
In addition, a method for fabricating the semiconductor package includes forming predetermined conductive wire patterns to a lower surface of an insulation film; forming first and second openings at the insulation film to at least partially expose the conductive wire patterns; attaching end portions of the conductive wire patterns formed under the first openings to corresponding chip pads; filling the first openings with an filling material; and attaching external terminals onto the corresponding conductive wire patterns exposed to the second openings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide and further explanation of the invention as claimed.